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Objective:
Inventing New Electronic products for development
of India in core sectors
Work Profile:
Memory Compiler (High Speed and High Density SRAMs and Register Files, ROM) development for leading foundries
from specs to delivery. Mainly memory circuit design related to margin & performance improvement, variability analysis
and functional verification.
Making project plan, resource scheduling, Mentored and trained junior engineers. Developed almost all of the
data validation flows , included in these are procedures to verify timing data, power data, leakage and area estimation. Working closely with Layout teams for design implementation.
Managing
the effort across multiple remote sites and cross functional teams to ensure the correct project execution.
Exposure on FINFET technology on 16nm and 14nm process node.
Margin &
performance improvement, variability analysis and functional verification.
Specialties:
•Bitcell & SenseAmp statistical analysis.
•Designing leafcells ,instance schematics design & their functional verification.
•Writing timing, power, leakage data measurements.
•Proposed & implemented design changes & optimization
•Supervised Layout team for all leafcells design & instance reliability issues
•Very good knowledge of Layout issues, floor planning of critical signals & power lines.
•Various Margin analysis & design fixes.
•Working with cross-border teams.
1.Education:-
- M.Tech (Integrated Electronics
and Circuits-VLSI Design) From IIT-Delhi
CGPA:3rd Sem:-8.45, 2nd Sem:-8, 1st Sem:-7.33 and Overall:-~8
(Among the top 3 rankers of the branch)
- B.Tech. in Electronics and Communication Engineering
from IET-Kanpur.
CGPA:
1st year : 9.75/10
2nd year: 10/10
3rd year: 9.83/10
4th year: 10/10
Overall: 9.9/10
(Among the top three rankers of the institute)
2. Field of Interest :
VLSI circuit design, Microelectronics, CAD for VLSI & VLSI Architectures
for Computer Networks
3.
Acadmic Projects and Assignments done :
- Cycle Accurate VHDL Model of 8085
- OP-AMP Design
- IC Technology: Presentation on Silicon Carbide
Technology
- VLSI Physical Design Lab: Low Ground Bounce
Output Buffer Design
- Simulated Anneling Based Standard Cell Placement
Algorithm
- Mixed Signal Term Paper
- Differential Amplifier Design and it's Modification to Modem
(in B.Tech.)
Mentor: Dr. P.K.Chatterji (IIT-Kanpur)
- Design of Modified Booth Multiplier :
A
single precision floating point multiplier was designed using Cadence schemetic tool.
Mentor:
Prof. G.S.Visweswaran(IIT- Delhi)
- Adaptive Delta Modulator Design (B.Tech.
Project at IET-Kanpur)
- MOSFET channel length extraction:
principles and methods ( Guide : Dr.M.Jagadeesh Kumar - IIT Delhi )
This paper discusses about the needs and principles for MOSFET channel length extraction at sub-micron regime. The paper
also discusses about the physical interpretation of channel length for Technological CAD modeling. This presentation was based
on the paper by Taur (in IEEE T.ED Dec 2000)
4. Final
Project:
My final semester M.Tech project was
on Low Power Design of Decimation Filter for Sigma-Delta A/D Converter.
Mentors: Prof. G.S.Visweswaran ( IIT-D ) &
Prof. Basbi Bhaumik (IIT-D)
(Links to all my projects and assignments report are underconstruction)
5. Courses taken in M.Tech :
Microelectronics
- IC Technology
- Analog Circuit Design
- Digital IC
- Digital Signal Processing
- MOS LSI
- Mixed Signal Circuit Design
- CAD of Digital systems
- CAD for VLSI design
- Analog fault Diagnosis
Physical Design Lab.
6. Achievements :
- Second Topper in B.Tech. Degree exam at Institute
Of Engineering & Technology(IET),Kanpur with a CGPA of 9.9 on scale of 10 .
- Got selected for M.Tech in IEC Branch
of IIT-Delhi (An esteemed branch of esteemed institute)
- Second Position holder of M.tech in IEC
Branch at IIT-Delhi
- Many award and recognition certificate winner
at Synopsys, Virage Logic and at NeoMagic.
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7. Interests :
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8. Industry Exposure:
I started my
career in semiconductor industry as a back-end Design Engineer just after completing the M.Tech in Integrated electronics
& circuits( VLSI- Design) from IIT Delhi in January 2003.
Presently I am working in Synopsy. Synopsy is market leader in providing advanced embedded memory
intellectual property (IP) for the design of complex integrated circuits. Here I am working in High
Density Memory development group. Virage provides a good platform to work on cutting edge technologies ranging from 14nm(FINFET),
28nm, 40nm, 65nm.............and implementation of submicron solutions to optimize design for Noise, Power & Leakge.
Previous to join Synopsys I was with
Virage Logic which was acquired by Synopsys on 2010. Before Virage Logic I was with NeoMagic Semicondutor as a back-end Design
Engineer.There I got exposure of different levels
of chip design from front end to back-end design. I was in the team which was
responsible for the development of MiMagic6 processor which was based on ARM9 core.There I got exposure to different levels of application processor design. I was also responsible for Mixed-Vt
library development to optimize core for low power & high speed. Instead of back-end work, I also got some opportunities
to work for front-end projects like study & implementation of AMBA(Advanced Microcontroler Bus Architecture)Bus
protocol and writing RTL & testbench(In Verilog) for AMBA-AHB 64bit to 32 bit Interface, writing RTL & testbench for AMBA-EHB( EHB is proprietary of NeoMagic and is enhanced
version of AHB bus protocol towards AXI bus protocol) interface.
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